The VPX3201 is a 3U OpenVPX™ board based around a Xilinx Kintex® UltraScale™ FPGA. It has two banks of DDR4 memory, for a total of 8GB of RAM (default configuration). Each bank is 72-bit wide – 64-bits of data plus ECC. Depending on the application, each bank can be used separately, or chained together into one 128-bit wide databus.

Using the front FMC slot, the card can be flexibly expanded with additional features as needed for a given application, such as storage, analogue or digital I/O. The FMC slot is VITA 57.1 compliant.

The card is available with an optional rear optical module, for up to 50Gbit/s of optical data transfer to the backplane. This module is compatible with the VITA 66.5 standard and is connected to the FPGA via four GTH serial transceivers. The backplane interface includes up to eight PCIe Gen3 lanes (8GT/s). These can be configured as 1x 8 lanes or as 2x 4 lanes. Furthermore two GTH serial interfaces are present. A switch chip can select two extra GTH serial interfaces, at the expense of PCIe lanes.

Additionally, a significant number of LVDS signals are routed from the FPGA directly to the backplane, for any other digital I/O needs.